1. Field of the Invention
The present invention relates to a thin film magnetic memory device, and more particularly to a thin film magnetic memory device provided with a memory cell having a magnetic tunnel junction (MTJ) and a semiconductor integrated circuit device including the thin film magnetic memory device as one of circuit blocks.
2. Description of the Background Art
MRAM (Magnetic Random Access Memory) devices have obtained attention as memory devices that can store nonvolatile data while consuming low power. An MRAM device is a memory device using a plurality of thin film magnetic materials formed in a semiconductor integrated circuit for storing nonvolatile data and for allowing random access to the respective thin film magnetic materials.
In particular, rapid progress in the performance of MRAM devices due to the use of a thin film magnetic material, wherein a magnetic tunnel junction is utilized, as a memory cell has been announced in recent years in, for example, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell” by Roy Scheuerlein, et al., 2000 IEEE ISSCC Digest of Technical Papers, TA7.2 and in “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” by M. Durlam, et al., 2000 IEEE ISSCC Digest of Technical Papers, TA7.3.
FIG. 39 is a schematic diagram showing the configuration of a memory cell (hereinafter, simply referred to as an MTJ memory cell) having a magnetic tunnel junction.
With reference to FIG. 39, the MTJ memory cell includes a tunneling magneto-resistance element TMR wherein the electric resistance changes in accordance with the data level of the memory data that has been magnetically written in and an access transistor ATR. Access transistor ATR is connected between a bit line BL and a source line SL so as to be in series with tunneling magneto-resistance element TMR. Typically, a field-effect transistor is utilized as access transistor ATR.
A bit line BL for allowing a data write current and a data read current to flow at the time of data write and data read, respectively, a write digit line WDL for allowing a data write current to flow at the time of data write, a word line WL for indicating data read and a source line SL for pulling tunneling magneto-resistance element TMR down to ground voltage GND at the time of data read are provided as wires directly affecting the MTJ memory cell.
FIG. 40 is a schematic diagram for describing the data write operation to the MTJ memory cell.
With reference to FIG. 40, tunneling magneto-resistance element TMR has a magnetic layer FL (hereinafter, simply referred to as a fixed magnetic layer FL) having a fixed direction of magnetization and a magnetic layer VL (hereinafter, simply referred to as a free magnetic layer VL) that is magnetized in the direction in accordance with a data write magnetic field generated by a data write current. A tunneling barrier TB formed of an insulating film is provided between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as, or in the opposite direction to, (positive direction or negative direction) fixed magnetic layer FL in accordance with the level of memory data to be written in.
The electric resistance of tunneling magneto-resistance element TMR changes in accordance with the relative relationships between fixed magnetic layer FL and free magnetic layer VL in regard to the direction of magnetization. Concretely, the electric resistance is reduced in the case where the directions of magnetization for fixed magnetic layer FL and free magnetic layer VL are the same in comparison with the case wherein the directions of magnetization for fixed magnetic layer FL and free magnetic layer VL are opposite to each other.
A strap SRP formed of a conductive material is formed as a lower layer of tunneling magneto-resistance element TMR in order to electrically couple tunneling magneto-resistance element TMR and access transistor ATR.
Word line WL is inactivated at the time of data write so that access transistor ATR is turned off. In this condition, a data write current for magnetizing free magnetic layer VL is made to flow in the direction in accordance with the level of write data through bit line BL and through write digit line WDL, respectively. That is to say, the direction of magnetization of free magnetic layer VL is determined by the direction of the data write current flowing through bit line BL and through write digit line WDL, respectively.
FIG. 41 is a conceptual diagram showing the relationship between the data write current and the condition of magnetization of the MTJ memory cell.
With reference to FIG. 41, lateral axis H (EA) indicates a magnetic field applied to free magnetic layer VL within tunneling magneto-resistance element TMR in the easy axis direction. On the other hand, longitudinal axis H (HA) indicates a magnetic field influencing free magnetic layer VL in the hard axis direction. Magnetic fields H (EA) and H (HA), respectively, correspond to two magnetic fields generated by currents flowing through bit line BL and through write word line WWL, respectively.
The direction of fixed magnetization of fixed magnetic layer FL is along the easy axis while free magnetic layer VL is magnetized in the (same) direction parallel to fixed magnetic layer FL or in the (opposite) direction anti-parallel to fixed magnetic layer FL along the easy axis in the MTJ memory cell. In the following, the electric resistances of tunneling magneto-resistance element TMR corresponding to the two magnetic directions of free magnetic layer VL, respectively, are denoted as R1 and R0 (here R1>R0) in the present specification. The MTJ memory cell can store data of one bit (“1” and “0”) corresponding to these two magnetic directions of free magnetic layer VL.
The magnetic directions of free magnetic layer VL can be rewritten only in the case where the sum of applied magnetic fields H (EA) and H (HA) reach to the region outside of the asteroid characteristics curves shown in FIG. 41. That is to say, in the case where the applied data write magnetic field has an intensity corresponding to a region inside of the asteroid characteristic curves, the magnetic direction of free magnetic layer VL does not change.
As shown in the asteroid characteristic curves, the magnetization threshold value required to switch the magnetic direction along the easy axis can be lowered by applying a magnetic field in the direction of the hard axis to free magnetic layer VL.
In the case where the operational point at the time of data write is set as in the example of FIG. 41, the data write magnetic field in the direction of the easy axis is set so that the intensity thereof becomes HWR in the MTJ memory cell, which is the object for data write. That is to say, the values of the data write currents flowing through bit line BL and through write word line WWL are set so that this data write magnetic field HWR can be obtained. In general, data write magnetic field HWR is shown as the sum of switching magnetic field HSW required for switching of the direction of magnetization and the amount of margin ΔH. That is to say, the equation HWR=HSW+ΔH holds.
FIG. 42 is a conceptual diagram for describing data read from the MTJ memory cell.
With reference to FIG. 42, access transistor ATR turns on in response to the activation of word line WL at the time of data read. Thereby, tunneling magneto-resistance element TMR is electrically coupled to bit line BL under the condition wherein tunneling magneto-resistance element TMR is pulled down to ground voltage GND. In this condition, a data read current Is is made to flow through a current path that includes bit line BL and tunneling magneto-resistance element TMR and, thereby, a change in voltage in accordance with the electric resistance of tunneling magneto-resistance element TMR, that is to say, in accordance with the level of the storage data of the MTJ memory cell, can be effectuated in bit line BL. In the case where, for example, data read current Is is started to be supplied after bit line BL has been precharged to a predetermined voltage, the storage data of the MTJ memory cell can be read by sensing the voltage of bit line BL.
FIG. 43 is a structural diagram of the MTJ memory cell fabricated in a semiconductor substrate.
With reference to FIG. 43, access transistor ATR formed in a semiconductor main substrate SUB has source/drain regions 310 and 320, which are n-type regions, as well as a gate 330. Source/drain region 310 is electrically coupled to source line SL via a metal film formed in a contact hole 341.
Write digit line WDL is formed in a metal wire layer provided as a layer above source line SL. Tunnel magnetic resistance element TMR is arranged on the upper layer side of write digit line WDL. Tunnel magnetic resistance element TMR is electrically coupled to source/drain region 320 of access transistor ATR via strap SRP and via a metal film formed in contact hole 340. Strap SRP is provided in order to electrically couple tunneling magneto-resistance element TMR to access transistor ATR and is formed of a conductive material.
Bit line BL is provided on the upper layer side of tunneling magneto-resistance element TMR and is electrically coupled to tunneling magneto-resistance element TMR via a buffer layer BFF. As described above, it is necessary to make data write currents flow through both bit line BL and write digit line WDL at the time of data write. On the other hand, word line WL is activated to be, for example, in the high voltage condition so that access transistor ATR is turned on at the time of data read. Thereby, the tunneling magneto-resistance element that has been pulled down to ground voltage GND via access transistor ATR is electrically coupled to bit line BL.
Bit line BL, through which a data write current and a data read current are made to flow, as well as write digit line WDL, through which a data write current is made to flow, are formed using a metal wire layer. On the other hand, word line WL is provided in order to control the gate voltage of access transistor ATR and, therefore, it is not necessary to make a large current flow. Accordingly, generally, from the point of view of enhancement of integration, word line WL is formed of a polysilicon layer or of a polycide layer in the same wire layer as is gate 330 without the additional provision of an independent metal wire layer.
On the other hand, a variety of system LSIs (Large Scale Integrated Circuits) have been proposed in recent years wherein a memory device, such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), serving as one circuit block, as well as a circuit block having a logic function are mounted, in a mixed manner, on the same chip. Accordingly, in the case where the MRAM device is used in such a system LSI, it becomes necessary to adapt the structure of the MRAM device.
FIG. 44 is a schematic diagram for describing the entirety of the general configuration of a system LSI on which an MRAM device is mounted.
With reference to FIG. 44, a plurality of system LSIs 350 formed on the same wafer is cut along dicing lines, shown by thick lines, and divided into interval LSI chips. Each system LSI 350 includes a plurality of circuit blocks. These circuit blocks include an MRAM circuit block 360 having a function as an MRAM device as well as a peripheral circuit block. The peripheral circuit block is formed of a logic circuit 370 for directing the operation of MRAM circuit block 360 and an interface (I/F) circuit 365, such as an A/D (analog/digital) converter, for exchange of information and data between circuit blocks inside of system LSI 350 or between the system LSI and the outside thereof.
A memory cell array (hereinafter also referred to as “MTJ memory cell array”) wherein MTJ memory cells, as shown in FIGS. 39 to 43, are arranged in an integrated manner is arranged in MRAM circuit block 360. In FIG. 44, for example, an MTJ memory cell array is arranged in the hatched region.
MTJ memory cells are formed only in an MTJ memory cell array portion in MRAM circuit block 360 inside of system LSI 350 in the above described manner and, therefore, areas of high and low density of MTJ memory cells occur within a chip as a result of such placement. That is to say, MTJ memory cells are arranged in sequence in the center portion of the MTJ memory cell array, wherein the density is high, while the periphery portion of the MTJ memory cell array adjoins a region wherein MTJ memory cells are not arranged and, therefore, the density becomes low.
A problem arises wherein uniform manufacture of MTJ memory cells within a memory cell array becomes difficult because areas of high and low density occur when a plurality of MTJ memory cells is arranged in the same chip. In the following, this problem is described in detail.
FIGS. 45A to 45E are conceptual diagrams for describing the non-uniformity of the dimensions, forms and structures caused at the time of manufacture of MTJ memory cells due to high and low densities of MTJ memory cells. As is clear from the description below, such non-uniformity is noteworthy in, in particular, a tunneling magneto-resistance element TMR wherein a magnetic tunnel junction is formed.
With reference to FIG. 45A, a strap layer 410 that has been deposited is processed in accordance with the designed pattern formation and a strap SRP, shown in FIG. 43, is formed in step (a). Polysilicon or tungsten is used for strap layer 410.
Processing of strap layer 410 is, in general, carried out by means of etching in accordance with the design pattern. At the time of etching, however, the film at the time of removal of the resist after etching in a region (hereinafter also referred to as “low density region of the pattern”) having a low density of MTJ memory cells tends to become thin in comparison with that in a region (hereinafter also referred to as “high density region of the pattern”) having a high density of MTJ memory cells. As a result of this, non-uniformity occurs in the thickness of the finished strap SRP. Here, the high density region of the pattern corresponds to the center of the MTJ memory cell array while the low density region of the pattern corresponds to the border portion of the MTJ memory cell array.
Next, with reference to FIG. 45B, magnetic layers for forming tunneling magneto-resistance element TMR are formed in step (b) on strap SRP that has formed. That is to say, magnetic layers 420, 422 and 424 are layered, with buffer layers 425, 427 and 429 intervened therebetween, as layers above strap SRP formed in step (a). Magnetic layer 422 corresponds to fixed magnetic layer FL shown in FIG. 40 and magnetic layer 424 corresponds to free magnetic layer VL shown in FIG. 40. Magnetic layer 420 is formed of antiferromagnetic material which fixes the direction of magnetization of fixed magnetic layer FL. Buffer layers 425, 427 and 429 are formed of, for example, polysilicon.
Furthermore, a buffer layer 430 for forming buffer layer BFF, shown in FIG. 43, is formed on magnetic layer 424. As described above, buffer layer 430 is formed using a conductive material in order to electrically couple tunneling magneto-resistance element TMR and a metal wire that corresponds to bit line BL arranged as a layer above tunneling magneto-resistance element TMR.
As shown in the figure, non-uniformity between the heights of the magnetic layers and buffer layers formed over the high density region of the pattern and the heights of the magnetic layers and buffer layers formed over low density region of the pattern occurs as a result of step (b). This is caused by the non-uniformity in the film thickness of strap SRP occurring in step (a).
Next, with reference to FIG. 45C, a resist film 440 is additionally applied to form a layer above the buffer layers and the magnetic layers layered in step (b) and is selectively removed in accordance with the structural pattern (memory cell pattern) of the MTJ memory cells in step (c). As a result or this, resist film 440 remains in the form corresponding to the memory cell pattern.
The buffer layers and the magnetic layers layered in step (b) are microscopically processed in accordance with the memory cell pattern by means of over etching along the remaining resist film 440. Thereby, tunneling magneto-resistance element TMR, shown in FIGS. 39 to 43, is formed. At the time of over etching, however, strap SRP, which has been formed as a thin layer, is further shaved in the low density region of the pattern and, in some cases, there is a possibility that strap SRP pattern may disappear.
In addition, the region to be removed and the region that is to remain in resist film 440 are, in general, selected by transcribing a mask pattern embodying the memory cell pattern to the resist film by means of exposure to light. Accordingly, in the “positive-type,” for example, wherein the resist film in the exposed portion remains, the width of the remaining resist film tends to be thicker than in the originally designed pattern due to interference and reflection of light used to expose the resist corresponding to the MTJ memory cells in the periphery in the low density region of the pattern. Contrarily, such reflection and interference of light do not occur in the low density region of the pattern and, therefore, the width of the remaining resist film becomes relatively thin. As a result of this, non-uniformity in the planar memory cell form occurs between the high density region of the pattern and the low density region of the pattern in the above described manner.
With reference to FIG. 45D, an interlayer insulating film 450 is formed over tunneling magneto-resistance element TMR that has been processed in accordance with the memory cell pattern in step (d) shown next.
Next, with reference to FIG. 45E, a planarization process by means of chemical mechanical polishing (CMP) is carried out on interlayer insulating film 450 and buffer layer 430 in step (e) and, after that, a metal wire layer 460 is formed. Metal wire layer 460 is formed of, for example, a Cu wire and corresponds to bit line BL shown in FIGS. 39 to 43. As described above, bit line BL is electrically coupled to tunneling magneto-resistance element TMR by means of buffer layer BFF.
There is a risk, however, wherein buffer layer 430 in an MTJ memory cell in the high density region of the pattern may be excessively shaved due to the effects of a step that occurs between the high density region of the pattern and the low density region of the pattern at the time of polishing of buffer layer 430 in the planarization process. Thereby, there is a danger of defective electrical coupling (fluctuation in electric resistance) between tunneling magneto-resistance element TMR and bit line BL as well as a danger of negative effects to the magnetic layers of which tunneling magneto-resistance element TMR is formed.
As described above, in the case where a region having a high density of MTJ memory cells and region having a low density of MTJ memory cells exist in a mixed manner within the same chip, a certain degree of non-uniformity in the forms and dimensions of MTJ memory cells inevitably occurs between these regions. Accordingly, a design that takes such a problem into consideration becomes necessary for an MRAM device and a system LSI, or the like, wherein an MRAM device and other devices are mounted in a mixed manner.
In addition, the steps of magnetization of fixed magnetic layer FL in a predetermined direction, shown in FIGS. 39 to 43, are always included in a manufacturing process for an MRAM device. Accordingly, it is necessary for the improvement of the manufacturing process to make the magnetic field application apparatus utilized in such magnetization steps compact and efficient.
Furthermore, as shown in FIG. 42, data write to an MTJ memory cell is carried out by application of a magnetic field that exceeds a predetermined intensity. Accordingly, there is a risk wherein erroneous data write may take position due to the occurrence of magnetic noise in a memory cell other than the selected memory cell that has been selected as the object of data write.
In particular, there is a high risk of erroneous data write to a group of non-selected memory cells belonging to the same row or the same column as the selected memory cell due to an overlap of magnetic noise because either the easy axis (EA) or the hard axis (HA) of this group of non-selected memory cells is subject to a data write magnetic field of a predetermined intensity. Accordingly, it is necessary to take into consideration layout rules for wire groups that become the source of such magnetic noise in an MRAM device.